1. Field of the Invention:
The present invention relates to the operation control system of an electronic computer and, more particularly to the operation control system of a micro-computer.
2. Description of the Prior Art:
Advances in semiconductor integration technology have had a great impact on the field of electronic computers. One of these impacts is the large scale integration (LSI) of the logic elements constituting an electronic computer. Rapid strides in performance have been proven by a number of electronic computers already developed. Another impact is the LSI of the electronic computer itself. This measure has attracted attention as a chief section of future electronic computers conjointly with the development of new fields of application.
Since with a micro-computer, an operation control unit is integrated into one to several packages, the overall construction of the system requires various forms. More specifically, the micro-computer formed by LSI techniques is naturally restricted by the chip size (the degree of integration), the package size (the number of terminals), operating speed and power dissipations of elements, etc. It is, therefore, necessary to develop an overall system layout which solves these restrictions. Further in forming the system, it must be carefully considered that satisfactory function inspections be made with a limited number of terminals.
When the chip size of the LSI circuit is large, the yield of the product becomes inferior, and the cost becomes high. The chip size should accordingly, be fit for present integration techniques by taking the optimum degree of integration into consideration. Since the chip size and, accordingly, the degree of integration, is restricted in this manner, it is often difficult to form the operation control unit of the micro-computer in a single chip.
In order to solve this problem, the operation control unit may be divided and formed in a plurality of chips. In this case, the manner in which the operation control unit is divided must be considered in association with the number of package terminals. The number of package terminals is limited, and yet, terminals for supplying signals from and delivering signals to external input and output equipment, a main memory, etc., terminals for various control signals and timing signals, power supply terminals, and so forth, are indispensible. Delivery and reception of signals between the respective chips must, therefore, be effected with the remaining terminals.
The performance of the micro-computer is restricted by the operating speeds of the constitutent elements. The operating speed is determined in association with the power dissipation in dependence on the speed-power product of the element for use. That is, the upper limit of the number of gates to be integrated is determined by the operating speed and the allowable power loss which is determined by the heat radiating capacity of the package for use. Consequently, for enhancing performance, the micro-computer must employ a logic construction in which the number of gates is minimized.
To be further considered in determining the overall layout of the micro-computer is that the logic construction must be employed with which satisfactory function tests can be executed among the limited number of terminals and which facilitates the tests in the system construction.